Arista 7130E Series

The Arista 7130E Series is a 1RU network appliance that installs three Xilinx UltraScale+ FPGAs into a chassis that also contains a full Layer 1 switch fabric and 48 10GbE SFP+ ports. The appliance is designed for workloads where the classification, inspection, or transformation of network traffic must happen at hardware speeds, at the Layer 1 latency of the switch fabric rather than in a software data plane that adds microseconds of processing delay. The three FPGAs are interconnected through multiple dedicated communication paths that also connect to the Ethernet ports, allowing FPGA logic to inspect, modify, and forward traffic between any combination of in-network FPGA processing and physical network ports without those packets leaving the appliance chassis and traversing an external network segment. The operating system is either MOS (Metamako Operating System) or EOS, both Linux-based, providing the enterprise device management capabilities (authentication, NTP, syslog, SNMP) expected from production network infrastructure rather than the bare management interfaces typical of custom FPGA appliances.

The 7130E addresses the density gap left by the earlier 7130K Series, providing three times the logic cell count and eight times the DSP slice count in the same 1RU form factor. This capacity increase allows larger and more complex FPGA applications to be implemented, such as multi-stage packet inspection pipelines, stateful connection tracking, or parallel processing across all three FPGAs simultaneously, that would exceed the resources available on the 7130K. The per-port Ethernet statistics and monitoring telemetry cover every port in the 7130-48E variant, providing continuous observability of traffic volumes and error rates across all 48 SFP+ interfaces without requiring a separate monitoring appliance or an out-of-band probe. For security-oriented deployments, the telemetry data allows the detection of anomalous traffic patterns such as port scans, unusual flow sizes, and unexpected protocols, without the FPGA application itself needing to export those observations.