2RU Layer 1+ FPGA switch with 5-6 ns latency, Xilinx Virtex UltraScale+ FPGA, 32 GB DDR DRAM, dynamic port patching, and onboard x86 server for in-network application hosting.
The Arista 7130LS Series is a 2RU platform that extends Layer 1 switching with an onboard Xilinx Virtex UltraScale+ VU7P FPGA and an integrated x86_64 server, creating a combined Layer 1 fabric, programmable compute, and server compute resource in a single chassis. The Layer 1 crosspoint operates at 5 nanoseconds for 48-port models (7130-48LS and 7130-48LAS) and 6 nanoseconds for 96-port models (7130-96LS and 7130-96LAS), with the FPGA holding 32 GB of DDR DRAM for stateful in-network processing. Dynamic patching replaces the need to physically rewire cabling when topology changes are required: port connections are reconfigured through software in the management layer, and the Layer 1 crosspoint implements the new path immediately. Ad-hoc tapping allows a new monitoring tap to be inserted on any port without disrupting the traffic in flight on that port, which is the operational distinction between Layer 1 tapping and Layer 2 SPAN that requires configuration changes with associated forwarding disruption.
The MultiAccess (LAS) variants add a 55 ns MultiAccess path that allows the FPGA and the external network to share access to the same Layer 1 connections, enabling scenarios where both the in-network FPGA application and an external host need to communicate over the same physical links without separate connections for each. MetaMux operates at 43 ns across all variants, providing a multiplexed access mode for applications that require multiple logical connections to be aggregated over shared physical links. Layer 1+ statistics on every link give continuous per-port signal quality and utilisation visibility, and media conversion allows the 7130LS to bridge between different optical standards within the same forwarding path. The throughput range of 100 Mbps to 11.3 Gbps per lane spans the range from legacy 1G connectivity to 10G line rate, making the 7130LS applicable to both legacy infrastructure integration and current 10G deployment environments.
Traditional Layer 1 optical patch panels require a field technician to physically move fibre cables when topology changes are needed, a process that is slow, error-prone, and impossible to perform remotely. The 7130LS implements dynamic patching through software, allowing any port to be connected to any other port in the crosspoint matrix by changing a configuration entry rather than moving a cable. For co-location environments where topology changes are frequent and the cost of dispatching a technician to move a cable is high, software-controlled patching replaces that operational overhead with a management command. The change takes effect at the Layer 1 crosspoint without any traffic disruption on other ports, and without the Layer 2 MAC table flush that a physical cable move would trigger on a traditional switch.
The 7130LS can insert a monitoring tap on any active port, replicating the traffic on that port to a monitoring destination, without interrupting the traffic in flight. Traditional passive optical tapping requires a physical tap coupler to be inserted in the fibre path, which requires the link to be taken down briefly to install the coupler. Layer 1 software tapping on the 7130LS requires only a configuration entry: the crosspoint replicates the signal from the tapped port to both its original destination and the monitoring destination simultaneously, with no physical intervention and no link interruption. For security monitoring or capacity planning use cases where the need to tap a link may not be known in advance, ad-hoc tapping provides the ability to add visibility to any port in the 7130LS fabric at any time without scheduling a maintenance window.
The Xilinx Virtex UltraScale+ VU7P Speed Grade 2 FPGA provides the reconfigurable compute fabric for in-network application acceleration, with 32 GB of DDR DRAM for state tables and buffers that exceed on-chip BRAM capacity. The VU7P is deployed here at Speed Grade 2, which provides the timing margin to implement logic within the 5-6 ns Layer 1 forwarding window while maintaining adequate setup and hold margins at FPGA operating frequencies. The FPGA is connected to the Layer 1 crosspoint through 2 internal 10G ports, providing the high-bandwidth, low-latency path between the FPGA logic and the physical network without routing traffic through external cables or an upstream switch. Applications are deployed as bitstream configurations, allowing the FPGA function to be changed without replacing hardware.
Every port in the 7130LS fabric generates continuous Layer 1+ statistics (signal level, error rate, utilisation, and link quality metrics) that are accessible through the management interface without affecting forwarding latency. This per-port telemetry provides the observability required to detect a degrading link before it fails, identify a port being driven at or near its rated throughput, or verify that a media conversion is operating within spec after a fibre plant change. The telemetry data is timestamped and exportable, making it available to network monitoring systems that aggregate link health data across the 7130S/LBR/LS fabric. Layer 1+ statistics differ from the interface counters available on standard Ethernet switches in that they operate below the Ethernet framing layer, providing signal-level measurements that are not visible to standard SNMP interface polling.
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