Arista 7130LBR Series

The Arista 7130LBR Series combines two Xilinx UltraScale+ VU9P-3 FPGAs with an integrated R-family merchant-silicon switch element in a single 1RU chassis, targeting deployments where in-network compute (order matching, market data normalisation, risk pre-screening) needs to execute at Layer 1 latency rather than as a separate compute step after forwarding. The FPGA portion of the design provides the reconfigurable logic required to implement custom in-network algorithms in hardware, while the integrated R-family switch delivers 1.5 Tbps of L2/L3 forwarding capacity across 48 SFP+/SFP28 ports and 6 QSFP-DD interfaces, totalling 96 independent 10/25G lanes. The Layer 1 crosspoint carries traffic between ports at 4 nanoseconds on the 10G variant (48S6QD) and 5 nanoseconds on the 25G variant (48S6YD), with the FPGA able to inspect, process, and act on the in-flight data within that forwarding window.

Each FPGA is equipped with 32 GB of DDR4 DRAM, providing the high-bandwidth memory required for table lookups, order book maintenance, and other state-dependent operations that exceed FPGA on-chip BRAM capacity. The 4 GB packet buffer shared across the platform handles burst absorption when the in-network application needs brief additional processing time without dropping packets. The QSFP-DD interfaces support breakout to 2x40GbE or 8x10/25GbE per port, giving the 7130LBR flexible connectivity for both high-density 10/25G access links and 40/100G uplink aggregation within the same 1RU chassis. Two hardware variants address the most common speed requirements: 48S6QD for 10G lane deployments where 4 ns latency is the primary constraint, and 48S6YD for 25G deployments where 5 ns latency across faster lanes is the requirement.